The present invention relates to dynamic random access memories, and more particularly to a method and system for hiding the refresh of such memories thereby allowing such memories to be accessed at any time.
Dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d) are commonly used as the system memory in computer systems. The DRAMs are typically coupled to a central processing unit (xe2x80x9cCPUxe2x80x9d) through a DRAM controller or bus bridge which is, in turn, coupled to the CPU through a processor bus. The DRAMs include one or more memory arrays each having a large number of memory cells arranged in rows and columns. Each memory cell of the DRAM requires only a single transistor and capacitor, thus making DRAMs very compact. The compact nature of DRAMs makes it possible for them to provide high memory capacities at relatively little cost.
Although DRAMs have the advantage of providing relatively high memory capacities at relatively little cost, they have the disadvantage of requiring periodic refresh of their memory cells. More particularly, since memory cells store data by charging their respective memory cell capacitors to predetermined voltages, their capacitors must be recharged or xe2x80x9crefreshedxe2x80x9d before excessive charge has leaked from the capacitors. During the time that the memory cells are being refreshed, data generally cannot be written to either the row of memory cells being refreshed or any other memory cells in the array. Further, although data may be read from a row of memory cells being refreshed, data generally cannot be read from other memory cells in the array. For many applications of DRAMs, such as for use as system memory, the need to periodically refresh the memory cells does not significantly limit their usefulness. However, the need to periodically refresh DRAMs generally makes them unsuitable for other applications, as described below.
Computer systems using DRAMs for system memory also frequently use a cache memory, which is normally coupled directly to the processor bus. The cache memory allows the CPU to more quickly access frequently or recently used instructions and data. Cache memories are generally implemented using static random access memories (xe2x80x9cSRAMsxe2x80x9d) that also have at least one array of memory cells. Each memory cell in the array is generally implemented by a pair of cross-coupled transistors, and each cell is accessed through a pair of access transistors. Each SRAM memory cell thus generally contains at least 4 transistors. As a result, SRAMs are far less compact than DRAMs and therefore significantly more expensive. However, SRAMs have a significant advantage over DRAMs in that their memory cells do not need to be periodically refreshed. As a result, SRAMs can be accessed by the CPU or other device at any time. In contrast, it would sometimes be necessary for the CPU or other device accessing a DRAM cache memory to wait until a refresh has been completed before the cache memory could be accessed. Therefore, despite their significantly higher expense, SRAM""s are generally considered more suitable than DRAMs for use as cache memory.
It would be desirable to use DRAMs for cache memory so that high capacity cache memory could be provided at relatively little cost. Attempts have been made to use DRAMs for cache memory, but these attempts have generally proven unsuccessful because of the inability to access them during periodic refreshes. For example, attempts have been made to implement cache memory using a high capacity DRAM and a significantly smaller SRAM to temporarily store write data during a refresh of the DRAM when the data cannot be written to the DRAM. While these attempts have been able to xe2x80x9chidexe2x80x9d refreshes of cache DRAMs under some circumstances, they have been unable to hide refreshes of DRAMs under at least some circumstances for a variety of reasons. Thus, these prior art cache DRAMs constrained computer systems using them in various ways, and their use often required that the computer system be specially modified for use with such cache DRAMs.
It would therefor be desirable to provide cache DRAMs that could truly hide the periodic refresh of their memory cells and which did not require special modifications of computer system, thus allowing such DRAMs to be pin compatible with cache SRAMS.
A dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), includes first and second arrays of memory cells each containing substantially the same data. A refresh circuit is structured to refresh the memory cells in either the first array or the second array, but not both. The refresh circuit is also structured to control access to one of the arrays as a function of which if any of the arrays is being refreshed. For a write access, the refresh circuit determines if either of the arrays is being refreshed. If one of the arrays is being refreshed, the refresh circuit allows data to be written to the array that is not being refreshed. The write data are also buffered until the refresh is completed, and are then written to the array that was being refreshed. Alternatively, the data can be later read from the array to which it was written and then written to the array that was being refreshed. If neither of the arrays is being refreshed, the refresh circuit allows data to be written to both arrays simultaneously. In either case, the refresh circuit also retains an indication of to which array(s) the data have been written, such as by setting a flag in a register. For a read access, the refresh circuit determines if either or both of the arrays contain valid data at locations corresponding to an address from which the data are to be read. The refresh circuit then allows data to be read from at least one of the arrays containing valid data. Since the refreshes are substantially hidden, the DRAM can be advantageously used as a cache memory in a computer system.